The present invention relates generally to manufacturing and, more particularly, to a method and apparatus for selecting sites for sampling.
A semiconductor fabrication facility typically includes numerous processing tools used to fabricate semiconductor devices. The processing tools may include photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal processing tools, ion implantation tools, and the like. Wafers (or wafer lots) are processed in the tools in a predetermined order and each processing tool modifies the wafers according to a particular operating recipe so that a desired product is formed in or on the wafer. For example, a photolithography stepper may be used to form a patterned layer of photoresist above the wafer. Features in the patterned layer of photoresist correspond to a plurality of features (e.g., gate electrode structures) that will ultimately be formed above the surface of the wafer. When processing of the wafer is complete, the various features formed in or on the wafer, as well as features formed in or on layers that are deposited above the wafer, combine to form the desired product. Exemplary products include processors, memory elements, and the like.
The semiconductor fabrication facility typically also includes metrology tools for collecting data indicative of the physical state of one or more wafers before, during, and/or after processing by the processing tools. Collecting the data indicative of the physical state of a wafer using a metrology tool is conventionally referred to as “sampling” the wafer. Data collected by the metrology tools may be used to characterize the wafer, to detect faults associated with the processing, and/or to determine (or predict) the quality of the finished product. For example, a mean critical dimension associated with the various features (e.g., gate electrode structures) may be indicative of a performance level of products formed on the wafer and/or the wafer lot. If the wafer state data indicates that the mean critical dimension associated with the feature (e.g., a gate electrode) is on the lower end of an allowable range for such feature sizes, then this may indicate that the product formed on the wafer may exhibit relatively high performance levels. For example, smaller feature sizes in a processor formed on the wafer may be associated with faster processing speeds. Higher performance products may be sold at a higher price, thereby increasing the profitability of the manufacturing operation.
High-volume semiconductor fabrication facilities may process hundreds or even thousands of wafer lots every week. Sampling every processed wafer (or wafer lot) may significantly reduce the efficiency of the semiconductor fabrication facility, at least in part because metrology generally takes longer than processing. Accordingly, only a portion of the wafers processed in the facility are typically sampled. For example, a wafer lot including 25 wafers may be processed using a three-chamber etching tool. To monitor the operation of each chamber of the etching tool, an engineer may select particular wafers in a run to be sampled by a metrology tool and include these selections in a sampling plan. If the wafers are provided to the chambers of the etching tool sequentially, one possible sampling plan could be to perform metrology on the first wafer, which should be provided to the first chamber, on the 11th wafer, which should be provided to the second chamber, and on the 24th wafer, which should be provided to the third chamber.
Moreover, it is not feasible to sample each die location on a selected wafer. It is known that certain characteristics vary across the wafer due to non-uniform processing. For example, an etch tool or chemical mechanical planarization (CMP) tool may vary radially, such that the process rate is greater nearer the center of the wafer or nearer the periphery of the wafer. Hence, a plurality of sites in different locations on the wafer is selected for sampling. Typically, the locations of these selected sites are fixed. Depending on the degree of oversight required for the product, the number of fixed sites may vary. For instance, 5, 9, or 17 sites may be sampled on a wafer.
Static sampling plans, such as the one described above, are appropriate as long as the manufacturing environment in the semiconductor fabrication facility is also static. With respect to site-level sampling, the predetermined site locations provide a fixed view of wafer uniformity. Uniformity variations in directions not addressed by the predetermined sample sites are not apparent from the collected metrology data.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the present invention described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the present invention. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.